DocumentCode
3435404
Title
Using MTBDDs for discrete timed symbolic model checking
Author
Kropf, Thomas ; Ruf, Jürgen
Author_Institution
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
fYear
1997
fDate
17-20 Mar 1997
Firstpage
182
Lastpage
187
Abstract
The verification of timing properties is an important task in the validation process of embedded and real time systems. Temporal logic model checking is one of the most successful techniques as it allows the complete automation of the verification. In this paper, we present a new approach to symbolic QCTL (Quantitative CTL) model checking. In contrast to previous approaches we use an intuitive QCTL semantics, provide an efficient model representation and the new algorithms require less iteration steps compared to translating the QCTL problem into CTL and using standard CTL model checking techniques. The new model checking algorithm is based on a MTBDD representation. Some experimental results show the efficiency of the new approach
Keywords
decision theory; diagrams; directed graphs; discrete time systems; formal verification; logic design; real-time systems; symbol manipulation; temporal logic; timing; MTBDD; QCTL semantics; algorithm; automation; discrete timed symbolic model checking; embedded system; iteration; multi-valued binary decision diagram; quantitative computation tree logic; real time system; temporal logic; timing properties; validation; verification; Automation; Boolean functions; Clocks; Data structures; Fault tolerance; Formal verification; Logic; Real time systems; State-space methods; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7786-4
Type
conf
DOI
10.1109/EDTC.1997.582356
Filename
582356
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