DocumentCode :
3436105
Title :
A constructive approach towards correctness of synthesis-application within retiming
Author :
Eisenbiegler, Dirk ; Kumar, Ramayya ; Blumenrohr, Christian
Author_Institution :
Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
427
Lastpage :
431
Abstract :
This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfils the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches
Keywords :
network synthesis; timing; algorithm; automation; circuit design; correct synthesis; retiming; rule applications; theorem prover; Algorithm design and analysis; Automation; Boolean functions; Circuit simulation; Circuit synthesis; Data structures; Fault tolerance; Formal verification; Hardware; Logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582395
Filename :
582395
Link To Document :
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