DocumentCode :
3436391
Title :
Low power FSM design using Huffman-style encoding
Author :
Surti, Prasoon ; Chao, L.F. ; Tyagi, Akhilesh
Author_Institution :
Intel Corp., Folsom, CA, USA
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
521
Lastpage :
525
Abstract :
This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively
Keywords :
Huffman codes; finite state machines; logic design; Huffman encoding algorithm; finite state machine; flip-flop; gated clock; limit state probability; low power FSM design; minterm; nonuniform code length; state set; switching activity; Automata; Chaos; Clocks; Design methodology; Encoding; Entropy; Huffman coding; Probability distribution; Sequential circuits; Signal generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582410
Filename :
582410
Link To Document :
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