Design considerations for fast-settling two-stage Miller-compensated operational amplifiers

The settling behavior of two-stage Miller-compensated operational amplifiers (op-amps) is investigated in this paper. The analysis aims to evaluate the real effectiveness of conventional design approaches for the settling performances optimization when op-amps are used in common SC circuits. It is shown that the existing strategies are effective only for sufficiently large values of the load capacitance to be driven by the SC circuit. In typical situations in which this condition is not satisfied, the conventional design rules to fix the element of the op-amp compensation network may be inadequate to achieve fast-settling two-stage amplifiers. Design examples in a commercial 0.35-¿m CMOS technology demonstrate that a careful strategy for the sizing of the amplifier compensation network elements can result in a significant reduction of the op-amp settling time with respect to designs in which the conventional criterion is used.