DocumentCode
3436746
Title
Simulation of reduced charge interference in 3-D vertical gate NAND flash memory
Author
Choi, Seonjun ; Lee, Junhyuk ; Oh, Seulki ; Lee, Seung-Beck
Author_Institution
Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
fYear
2010
fDate
24-26 Sept. 2010
Firstpage
140
Lastpage
144
Abstract
In this work, we propose two type of structures to reduce the charge interference by stored charge in the opposite side cell of a vertical gate 3-dimensional NAND flash memory. The first structure is a "barrier oxide" and the second is a "virtual ground". The barrier oxide physically blocks electrons moving by repulsive force from charge stored on the opposite cell. The virtual ground increases the energy band bending level close to the body region at the center and it blocks the effect of converged holes better then when only the barrier oxide was used. We investigated the I-V characteristics of the different structures at double programming or single programming. We used 3-D TCAD simulation tool and confirmed the effect of reduce charge interference by the proposed structures.
Keywords
NAND circuits; flash memories; logic CAD; technology CAD (electronics); 3D TCAD simulation tool; 3D vertical gate NAND flash memory; I-V characteristics; barrier oxide; energy band bending level; reduced charge interference; vertical gate 3-dimensional NAND flash memory; virtual ground; Body regions; Flash memory; Interference; Logic gates; Programming; Silicon; Threshold voltage; BICS; MONOS; VG NAND; Virtual ground; charge interference;
fLanguage
English
Publisher
ieee
Conference_Titel
Network Infrastructure and Digital Content, 2010 2nd IEEE International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-6851-5
Type
conf
DOI
10.1109/ICNIDC.2010.5657914
Filename
5657914
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