A 4th order CMOS 65nm wideband low power analog filter for wireless receivers

A 4^th-order continuous-time band-pass filter for wireless receivers is here presented. The filter is composed by the cascade of two active RC cells. The overall pass-band (32 dB) gain is distributed for each cell in order to minimize the power consumption. The operating point issues due to the low V_DD/V_TH ratio - a value of 2 is typical in CMOS 65 nm technologies and down - have been solved by adding a proper bias circuit to the filter. The f_@-3dB deviation due to the technological spread, aging and temperature in active RC circuits is adjusted by using variable capacitor with 4 bits of resolution. The device in 65 nm CMOS technology consumes 1.3 mW from a single 1.2 V supply voltage, features -10 dBm-IIP3 and 1.6 mV_rms output integrated noise over the pass-band - 300 kHz÷8 MHz.