Title :
Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors
Author :
Moens, P. ; Van den Bosch, G. ; Groeseneken, G.
fDate :
30 March-4 April 2003
Abstract :
In this paper, the hot carrier degradation behaviour of a lateral nDMOS, processed in a 0.35 μm compatible Smart Power Technology, is presented. It is shown that upon reverse bias stress, two different and competing degradation mechanisms occur. An attempt is made to identify the two mechanisms by analysis of the electrical data and by performing Charge Pumping (CP) experiments and TCAD simulations. A first mechanism is attributed to a decreased electron mobility due to increased carrier scattering upon Dit formation in the channel, whereas the second mechanism occurs in the gate overlapped drift region of the device and is due to hot-hole injection and trapping. The competition of both mechanisms depends strongly on the stress conditions. A model is presented.
Keywords :
CMOS integrated circuits; electron mobility; hole traps; hot carriers; impact ionisation; power MOSFET; power integrated circuits; semiconductor device models; semiconductor device reliability; technology CAD (electronics); 0.35 μm compatible smart power technology; 0.35 micron; CMOS compatible smart power technology; Dit formation; TCAD simulations; carrier scattering; charge pumping experiments; competing degradation mechanisms; electrical data; electron mobility; gate overlapped drift region; hot carrier degradation mechanisms; hot-hole injection; hot-hole trapping; lateral n-type DMOS transistors; model; reverse bias stress; stress conditions; CMOS process; Charge pumps; Degradation; Electron mobility; Electron traps; Hot carriers; Performance analysis; Scattering; Semiconductor device modeling; Stress;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197748
