New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

With SOCs being increasingly designed for communication and embedded processing applications, the content of analog, mixed-signal (AMS) and RF components in them has increased. Large SOCs are often dominated by these components, which in turn also contribute to the overall incurred test time, attainable test quality and time required for silicon debug and characterisation. Existing test methods based on the use of specification based tests and use of design verification test-benches are increasingly difficult to adopt in such SOCs (as compared to standalone IP chips) since a large number of such modules and their interactions must be tested in the budgeted test time. The paper describes the practical use of fault simulation for AMS circuits to address the above issues. The main contributions of this paper are two-fold. (i) Enhancements are proposed to a commercially available analog fault simulation flow to handle specific SOC requirements of accuracy and speed, using smart management of models and/or fault lists across different fault conditions and fault sites. (ii) Efficient test generation methods targeting the analog -- digital interface are built by identifying uncovered regions/operating modes of the circuit. These are novel extensions to the commercial analog EDA tools supporting regular fault simulation. Experiments are performed on industrial designs and benefits are highlighted. It is expected that such techniques will be increasingly required to be integrated into the design flows for mixed-signal SOCs.