Title :
Diagnostic Tests for Pre-bond TSV Defects
Author :
Bei Zhang ; Agrawal, V.D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
Pre-bond testing and defect identification of through silicon via (TSV) is extremely important for yield assurance of 3D stacked devices. Based on a recently published pre-bond TSV probing technique, this paper proposes an ILP (integer linear programming) model to generate near-optimal set of sessions for pre-bond TSV test. The sessions generated by our model identify defective TSVs in a TSV network with the same capability as that of other available heuristic methods, but with consistently reduced test time. The ILP model is shown to reduce the pre-bond TSV test time by 38.2% for pinpointing up to two faulty TSVs in an 11-TSV network. Reducing prebond TSV test time helps reduce the manufacturing cost of 3D stacked devices. This ILP model has low complexity and an example demonstration using a commercial solver takes less than 40 seconds.
Keywords :
integer programming; integrated circuit bonding; integrated circuit testing; linear programming; three-dimensional integrated circuits; 3D stacked devices; ILP model; TSV network; defect identification; diagnostic tests; integer linear programming model; pre-bond TSV probing technique; prebond TSV defects; prebond TSV test time; prebond testing; through silicon via; Circuit faults; Electrical resistance measurement; Needles; Probes; Resistance; Testing; Through-silicon vias; 3D stacked integrated circuits; pre-bond TSV testing; through silicon via (TSV) defects;
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
DOI :
10.1109/VLSID.2015.71