DocumentCode :
3437976
Title :
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits
Author :
Pawanekar, S. ; Trivedi, G. ; Kapoor, K.
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol., Guwahati, Guwahati, India
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
423
Lastpage :
428
Abstract :
We present an analytical method to perform VLSI standard cell placement. We have developed a placement engine based on analytical methods that makes use of non-linear programming. At first we cluster a net list to reduce the number of cells. In the second step we perform quadratic optimization on the reduced net list. Finally we use conjugate gradient method for solving non-linear equations for the problem. The framework of our tool, Kapees2, is scalable and generates high quality results. We obtain results for IBM version 2 benchmarks which show promising results. Our placer outperforms Capo, Amoeba, NTUPlace3 and feng shui by 7%, 12%, 2% and 1%, respectively.
Keywords :
VLSI; conjugate gradient methods; integrated circuit design; nonlinear programming; Amoeba; Capo; IBM version 2 benchmarks; Kapees2; NTUPlace3; VLSI circuits; VLSI standard cell placement; conjugate gradient method; feng shui; nonlinear analytical optimization method; nonlinear equations; nonlinear programming; placement engine; quadratic optimization; reduced net list; Benchmark testing; Equations; Linear programming; Mathematical model; Optimization; Standards; Very large scale integration; Conjugate Gradient; Nonlinear Optimization; Standard Cell Placement; VLSI Placement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.77
Filename :
7031771
Link To Document :
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