VLSI support for copyback caching protocols on Futurebus

The author discusses the nature of the superset of copyback cache protocols described by the MOESI state model, the superset bus transactions of the Futurebus, and the complications encountered in an actual VLSI implementation. It has been shown that the Futurebus provides the best generic and standard solution to cost-effective interconnection of coherent copyback caches. Its fully compelled protocol and the ability to extend or abort transactions allowed the design of the cache controller to be much simpler and less subject to critical timing constraints that it would otherwise have been. The practical design details of the cache controller uncovered numerous coherence `holes´ involving data that is in transit in the fill or flush buffer, or that is partially within the SRAM (static random-access memory) array and partially within the fill buffer. These were solved by thinking of those buffers as one-line caches, with cache state (such as ownership) associated with them