DocumentCode :
3438224
Title :
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks
Author :
Mohammadi, M. ; Satpute, N. ; Ronge, R. ; Chandiramani, J.R. ; Nandy, S.K. ; Raihan, A. ; Verma, T. ; Narayan, R. ; Bhattacharya, S.
Author_Institution :
Indian Inst. of Sci., Bangalore, India
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
505
Lastpage :
510
Abstract :
Radial Basis Function Neural Networks (RBFNN) are used in variety of applications such as pattern recognition, control and time series prediction and nonlinear identification. RBFNN with Gaussian Function as the basis function is considered for classification purpose. Training is done offline using K-means clustering method for center learning and Pseudo inverse for weight adjustments. Offline training is done since the objective function with any fixed set of weights can be computed and we can see whether we make any progress in training. Moreover, minimum of the objective function can be computed to any desired precision, while with online training none of these can be done and it is more difficult and unreliable. In this paper we provide the comparison of RBFNN implementation on FPGAs using soft core processor based multi-processor system versus a network of Hyper Cells [8], [13]. Next we propose three different partitioning structures (Linear, Tree and Hybrid) for the implementation of RBFNN of large dimensions. Our results show that implementation of RBFNN on a network of Hyper Cells using Hybrid Structure, has on average 26x clock cycle reduction and 105X improvement in the performance over that of multi-processor system on FPGAs.
Keywords :
Gaussian processes; learning (artificial intelligence); multiprocessing systems; pattern clustering; radial basis function networks; time series; FPGA; Gaussian function; RBFNN; center learning; flexible scalable hardware architecture; hybrid structure; hyper cells; k-means clustering method; multiprocessor system; nonlinear identification; offline training; online training; pattern recognition; pseudo inverse; radial basis function neural networks; soft core processor; time series prediction; Clocks; Computer architecture; Euclidean distance; Generators; Hardware; Neurons; Training; Multi Processor System on Chip; Pattern Recognition; Radial Basis Function Neural Network; Reconfigurable Architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.91
Filename :
7031785
Link To Document :
بازگشت