Integrated design and test synthesis

An integrated design and test synthesis methodology is presented with area, delay, and test cost constraints. This methodology, called CATREE2, differs from other approaches by simultaneously synthesizing the normal and test mode design behavior. It is particularly suited for top-down system design where a VLSI component´s behavior and test method have been fully specified. Preliminary results show that better design solutions are obtained by considering test incorporation during design synthesis than other methods which incorporate test after a structural design solution is formed