Title :
Test technology 20 years and beyond
Author_Institution :
IBM Corp., Boulder, CO, USA
Abstract :
The author covers a number of developments in the area of design for testability. It begins with the ad hoc area of design for testability. This is followed by scan and self-test techniques. The new IEEE Standard for boundary scan is presented and it´s impact on testing is discussed. Having given an idea of the state of art in testing he then deals with future directions that this area is going in. The two main areas which are discussed are redundancy used in fault-tolerance and then the synthesis area
Keywords :
automatic test equipment; built-in self test; circuit CAD; fault tolerant computing; integrated circuit testing; logic testing; printed circuit testing; redundancy; IEEE Standard; boundary scan; design for testability; fault-tolerance; redundancy; self-test; synthesis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Logic testing; Neck; Pain;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257348
