DocumentCode :
3438790
Title :
Area and timing estimation for lookup table based FPGAs
Author :
Xu, Min ; Kurdahi, Fadi J.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
151
Lastpage :
157
Abstract :
The importance of efficient area and timing estimation techniques is well-established in High-Level Synthesis (HLS), since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specific tools on the design space. Much of previous work has focused on estimation techniques that use very simple cost models based solely on the gate and/or literal count. Those models are not accurate enough to allow effective design space exploration since the effects of interconnect can indeed dominate the final design cost. The situation becomes even worse when the design is targeted to Field Programmable Gate Array (FPGA) technologies since the wire delay may contribute up to 60% of the overall design delay. In this paper, we present an approach of estimating area and timing for lookup table based FPGAs that takes into account not only gate area and delay but also the wiring effects. We select Xilinx XC4000 series as our main concentration because of their popularity. We tested our estimator with several benchmarks and the results show that we can get accurate area and timing estimates efficiently
Keywords :
circuit CAD; delays; field programmable gate arrays; high level synthesis; integrated circuit layout; logic design; network routing; table lookup; timing; Xilinx XC4000 series; area estimation; design delay; design space exploration; field programmable gate array; gate area; high-level synthesis; lookup table based FPGAs; timing estimation; wiring effects; Costs; Delay effects; Delay estimation; Field programmable gate arrays; High level synthesis; Space exploration; Space technology; Table lookup; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494141
Filename :
494141
Link To Document :
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