Title :
Efficient self-timed circuits based on weak NMOS-trees
Author :
Jimenez, R. ; Acosta, A.J. ; Barriga, A. ; Bellido, M.J. ; Valencia, M.
Author_Institution :
Inst. de Microelectron. de Sevilla, Seville Univ., Spain
Abstract :
This communication presents two proposals of CMOS self-timed computation blocks. The main novelty lies on the use of weak (long and narrow) transistors to build the NMOS differential trees performing the logic functions. The most important advantage is that memory elements are not needed to store data when they are operating into a full-handshaking pipelined architecture, thus saving hardware
Keywords :
CMOS logic circuits; adders; integrated circuit design; logic design; parallel architectures; pipeline processing; timing; trees (mathematics); 1 mum; CMOS self-timed circuits; FIFO cell memory; NMOS differential trees; SODS; full custom layout; full-adder circuit; full-handshaking pipelined architecture; logic functions; long narrow transistors; self-timed computation blocks; switched output differential structure; synchronous VLSI CMOS; weak NMOS-trees; Circuits; Clocks; Computer architecture; Hardware; Logic functions; MOS devices; Proposals; Protocols; Timing; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.813962
