Title :
Optimized design of 4 stage Dickson voltage multiplier
Author :
Cataldo, G. Di ; Palumbo, G.
Author_Institution :
Dipartimento Elettrico, Electtronico e Sistemistico, Catania Univ., Italy
fDate :
30 May-2 Jun 1994
Abstract :
In this paper we develop a dynamic model for the 4 stage Dickson voltage multiplier. Starting from the model proposed, optimized design can be performed. The circuit discussed is commonly used in power ICs or memory to allow the switching on of an MOS device. The model proposed is validated both by measurement and SPICE simulation
Keywords :
circuit optimisation; network synthesis; power electronics; voltage multipliers; Dickson voltage multiplier; MOS device switch-on; SPICE simulation; dynamic model; four-stage multiplier; memory circuits; optimized design; power ICs; Capacitors; Clocks; Communication switching; Design optimization; Equations; MOS devices; Power integrated circuits; Power supplies; Switching circuits; Threshold voltage;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409468
