Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations

Author

Su, Y.N. ; Shieh, J.H. ; Tsai, J.S. ; Ting, C.Y. ; Lin, C.H. ; Chou, C.L. ; Hsu, J.W. ; Jang, S.M. ; Liang, M.S.

Author_Institution

Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsin-Chu

fYear

2005

fDate

5-5 Dec. 2005

Lastpage

88

Abstract

This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations

Keywords

copper; integrated circuit interconnections; low-k dielectric thin films; masks; nanotechnology; 32 nm; 45 nm; 65 nm; Cu; ash-free process; dual damascene fabrication; low-k dielectric; pore sealing technique; trench-first hard mask process flow; via-first PR mask process flows; Ash; Curing; Degradation; Dielectrics; Electric breakdown; Etching; Plasma applications; Plasma density; Resists; Silicon carbide;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609273

Filename

1609273