DocumentCode
3440907
Title
Performance of Yamakawa´s chaotic chips and Chua´s circuits for secure communications
Author
Itoh, Makoto ; Murakami, Hiroyuki ; Chua, Leon O.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Nagasaki Univ., Japan
Volume
6
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
105
Abstract
In this paper, we demonstrate how Yamakawa´s chaotic chips and Chua´s circuits can be used to implement a secure communication system based on chaotic modulation/demodulation systems. Furthermore, their performance for the secure communication is discussed
Keywords
Chua´s circuit; chaos; demodulation; discrete time systems; modulation; nonlinear dynamical systems; Chua´s circuits; Yamakawa´s chaotic chips; chaotic demodulation; chaotic modulation; discrete-time dynamical system; secure communication system; Chaotic communication; Circuits; Communication system security; Computer science; Delay lines; Demodulation; Equations; Modulation coding; Piecewise linear techniques; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409537
Filename
409537
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