An approach for online repair and yield enhancement of VLSI/WSI redundant memories

Author

Shen, Y.-N. ; Lombardi, F.

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

1991

fDate

13-16 May 1991

Firstpage

685

Lastpage

689

Abstract

A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty clusters and the practice of dividing a large memory into smaller subarrays (partitions) for speeding up the process of finding the overall repair-solution

Keywords

VLSI; circuit reliability; integrated circuit testing; integrated memory circuits; random-access storage; redundancy; VLSI/WSI redundant memories; divide-and-conquer; fault pattern; faulty clusters; online repair; partitions; row/column repair; subarrays; yield enhancement; Computer science; Costs; Manufacturing; Production; Random access memory; Read-write memory; Redundancy; Testing; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257472

Filename

257472