VLSI architecture for motion estimation using the block-matching algorithm

Author

Sanz, César ; Garrido, Matías J. ; Meneses, Juan M.

Author_Institution

Dept. de Sistemas Electronicos y de Control, Tech. Univ. of Madrid, Spain

fYear

1996

fDate

11-14 Mar 1996

Firstpage

310

Lastpage

314

Abstract

In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 μm double-metal-layer CMOS technology. This ASIC is cascadable to deal with bigger search areas

Keywords

CMOS digital integrated circuits; VLSI; block codes; digital signal processing chips; image coding; motion estimation; 0.7 micron; EST256 architecture; VLSI architecture; absolute value determination; accumulation; block-matching algorithm; comparison; double-metal-layer CMOS technology; exhaustive search method; image coding; motion estimation; search area; subtraction; Computer architecture; Coprocessors; Decoding; Discrete cosine transforms; HDTV; Image coding; Image storage; Motion estimation; Telecommunications; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494318

Filename

494318