High rate soft output Viterbi decoder

Author

Lüthi, Eric ; Casseau, Emmanuel

Author_Institution

Lab. for Integrated Circuits for Telecommun., Ecole Nat. Superieure des Telecommun. de Bretagne, Brest, France

fYear

1996

fDate

11-14 Mar 1996

Firstpage

315

Lastpage

319

Abstract

This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s, 8 states, R=1/2), using the “radix” trellis method to speed up the rate of a decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of “turbo-codes”, which are a class of convolutional codes whose performances in terms of bit error rate, are close to the Shannon limit

Keywords

Viterbi decoding; convolutional codes; digital communication; satellite communication; trellis codes; 100 Mbit/s; Shannon limit; Viterbi decoder; a posteriori weighting algorithm; bit error rate; convolutional codes; radix trellis method; satellite digital communication systems; soft output; turbo-codes; Artificial satellites; Bit error rate; Convolutional codes; Digital communication; High speed integrated circuits; Laboratories; Maximum likelihood decoding; Telecommunications; Turbo codes; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494319

Filename

494319