DocumentCode :
3441486
Title :
On test generation for interconnected finite-state machines-the output sequence justification problem
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
380
Lastpage :
385
Abstract :
Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback loops are included within the submachines. In this work, we describe a test generation procedure that takes advantage of cycle free circuit decomposition. The paper focuses on one of the subproblems of the test generation problem, the output sequence justification problem. We propose a solution to this problem and show how it can be incorporated into a test generation procedure
Keywords :
finite state machines; logic partitioning; logic testing; sequential circuits; cycle free circuit decomposition; feedback loops; interconnected finite-state machines; output sequence justification; submachines; synchronous sequential circuits; test generation; Circuit testing; Cities and towns; Feedback circuits; Feedback loop; Integrated circuit interconnections; Logic testing; Sequential analysis; Sequential circuits; State-space methods; Synchronous generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494329
Filename :
494329
Link To Document :
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