VLSI implementation of GSC architecture with a new ripple carry adder

Author

Reed, Irving S. ; Sharma, B. ; Shih, M.T. ; Bailey, John ; Truong, T.K.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

520

Lastpage

523

Abstract

The authors describe the VLSI implementation of a general sidelobe cancellor (GSC) using powers-of-two arithmetic. The chip needed for this design carries six multiplications and seven additions. The layout of this chip is based on the standard cell and regular structure approach. To reduce the propagation delay of its carry-save addition unit, a fast ripple carry adder which has a single NAND gate delay for carry propagation is designed. This adder is designed to reduce the propagation delay of carries by a factor of two

Keywords

VLSI; adders; delays; digital arithmetic; digital signal processing chips; additions; carry propagation; carry-save addition unit; fast ripple carry adder; general sidelobe cancellor; multiplications; powers-of-two arithmetic; propagation delay; standard cell; Clocks; Computer architecture; Matrix decomposition; Pins; Pipelines; Propagation delay; Shift registers; Switches; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25754

Filename

25754