Title :
Performance and limitations of 65 nm CMOS for integrated RF power applications
Author :
Scholvin, Jörg ; Greenberg, David R. ; del Alamo, Jesús A.
Author_Institution :
MIT, Cambridge, MA
Abstract :
In this study, we present the first measurements of the RF power performance of 65 nm CMOS for different voltages and layouts. We demonstrate that the 65 nm technology node is capable of achieving PAE values greater than 50% at 8 GHz, with Pout scalable to about 17 dBm. This is of interest for many applications. Greater performance is expected by optimizing the layout to minimize interconnect resistance
Keywords :
CMOS integrated circuits; integrated circuit interconnections; integrated circuit layout; microwave integrated circuits; 65 nm; 8 GHz; CMOS; RF power performance; interconnect resistance; CMOS technology; Costs; Fingers; Foundries; Gain; Logic devices; Power generation; Power measurement; Radio frequency; Voltage;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609353
