Title :
Error tolerance in parallel simulated annealing techniques
Author :
Jayaraman, Rajeev ; Darema, Frederica
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Abstract :
The authors present some statistical properties of the error introduced in a parallel annealing algorithm for placement. A general parallel algorithm model not specific to any target-machine implementation has been proposed. They have characterized the error in such a general parallel paradigm. Further, they have shown how this error varies with temperature for different parallel configurations. Specifically, they have shown the effect of stream length and the number of streams on the error. They have defined the parallelism factor to illustrate the comparative effects of the two configuration parameters. The effect of error on the convergence of the algorithm was observed. Experimental results are presented to demonstrate the effect of various parameters on the error
Keywords :
circuit layout CAD; convergence; error analysis; optimisation; parallel algorithms; convergence; error tolerance; parallel simulated annealing techniques; parallelism factor; placement; statistical properties; stream length; Application software; Computational modeling; Computer errors; Concurrent computing; Design automation; Error correction; Parallel algorithms; Parallel processing; Partitioning algorithms; Simulated annealing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25759
