Title :
On fault tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Wisconsin Univ., Milwaukee, WI, USA
Abstract :
The design of fault-tolerant array structures from non-fault-tolerant array structures is studied. It is shown how hardware redundancy can be used in existing structures to make them capable of withstanding the failure of some of the array elements. Then distributed fault-tolerance schemes are introduced for the diagnosis of the fault elements, reconfiguration, and recovery of the array after failure of some of the elements
Keywords :
VLSI; fault tolerant computing; matrix algebra; parallel processing; redundancy; system recovery; RECON-1 algorithm; array processors; distributed fault-diagnosis; fault-tolerant array structures; hardware redundancy; reconfiguration; Centralized control; Computer errors; Distributed control; Error correction; Fault diagnosis; Fault tolerance; Fault tolerant systems; Hardware; Redundancy; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25761
