DocumentCode :
3443512
Title :
The AMULET2e cache system
Author :
Garside, J.D. ; Temple, S. ; Mehra, R.
Author_Institution :
Dept. of Comput. Sci., Manchester Univ., UK
fYear :
1996
fDate :
18-21 Mar 1996
Firstpage :
208
Lastpage :
217
Abstract :
AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of levels in the design. For example, the cache is micropipelined to increase its throughput, at the architectural level there is an arbitration free non-blocking line fetch mechanism while at the circuit design level there is a power-saving RAM sense amplifier control circuit. A significant property of the cache system is its ability to cycle in a data dependent way which allows the system to approach average case performance
Keywords :
cache storage; memory architecture; microprocessor chips; AMULET2e; arbitration free non-blocking line fetch mechanism; asynchronous microprocessor; cache system; micropipelined; Circuit synthesis; Clocks; Computer science; Control systems; Energy consumption; Microarchitecture; Microprocessors; Random access memory; Read-write memory; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on
Conference_Location :
Fukushima
Print_ISBN :
0-8186-7298-6
Type :
conf
DOI :
10.1109/ASYNC.1996.494452
Filename :
494452
Link To Document :
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