DocumentCode :
3444836
Title :
Loop scheduling and partitions for hiding memory latencies
Author :
Chen, Fei ; Sha, Edwin Hsing-Mean
Author_Institution :
Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
fYear :
1999
fDate :
36465
Firstpage :
64
Lastpage :
70
Abstract :
Partition scheduling with prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is first divided into regular partitions. Then two parts of the schedule, the ALU part and the memory part, are produced and balanced to produce an overall schedule with high throughput. These two parts are executed simultaneously, and hence the remote memory latency are overlapped. We study the optimal partition shape and size so that a well balanced overall schedule can be obtained. Experiments on DSP benchmarks show that the proposed methodology consistently produces optimal or near optimal solutions
Keywords :
pipeline processing; program control structures; scheduling; software performance evaluation; DSP benchmarks; data prefetching; experiments; high throughput; loop pipelining; loop scheduling; memory latency hiding technique; partition scheduling; remote memory latency; Delay; Digital signal processing; Parallel processing; Partitioning algorithms; Pipeline processing; Prefetching; Processor scheduling; Scheduling algorithm; Shape; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Synthesis, 1999. Proceedings. 12th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0356-X
Type :
conf
DOI :
10.1109/ISSS.1999.814262
Filename :
814262
Link To Document :
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