Timing and Fast Control for the Upgraded Readout Architecture of the LHCb Experiment at CERN

The LHCb experiment at CERN has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The various subsystems in the readout architecture will be upgraded to cope with higher subdetector occupancies, higher rate, and higher readout load. We introduce here the new architecture, the new functionalities, and the first hardware implementation of the new LHCb Fast Readout Control system (S-TFC) for the upgraded LHCb experiment. Moreover, in this particular paper we focus our attention in describing solutions for the distribution of clock and timing information to control the entire upgraded readout architecture by profiting of a bidirectional optical network and powerful FPGAs, including a real-time mechanism to synchronize the entire system. Protocols and FPGA logic are also described, together with first results on the simulation and the validation of the system. This paper is a public excerpt of the technical documentation for the LHCb upgrade.