A systems approach for quality and reliability of chip scale package assembly

Author

Ghaffarian, Reza

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

Volume

2

fYear

1999

fDate

1999

Firstpage

289

Abstract

This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COTS) chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables. Methods of accelerated environmental testing were discussed and reasons for unrealistic life projections for CSP assembly reliability by numerous modelers is also examined. Preliminary thermal cycling test results in the range of -30°C to 100°C for test vehicles, especially a double sided assembly were also presented. It was concluded that availability of meaningful assembly reliability test results are needed to accelerate implementation of this technology. The JPL-led CSP consortia are addressing many of these issues

Keywords

ball grid arrays; chip scale packaging; concurrent engineering; environmental testing; integrated circuit interconnections; integrated circuit reliability; life testing; microassembling; -30 to 100 C; BGA; COTS chip scale package assembly; accelerated environmental testing; assembly quality; assembly variables; board design; concurrent engineering; double sided assembly; interconnect reliability; package build; package type; solder joints; systems approach; thermal cycling test; underfill; unrealistic life projections; Assembly systems; Benchmark testing; Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Laboratories; Life estimation; Life testing; NASA; Propulsion;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference, 1999. Proceedings. 1999 IEEE

Conference_Location

Snowmass at Aspen, CO

Print_ISBN

0-7803-5425-7

Type

conf

DOI

10.1109/AERO.1999.793173

Filename

793173