A novel design concept for small-skew clock LSIs with the self-delay-adjustment

A novel concept for ±50-ps-skew clock distribution LSIs for use in large computers is presented. The keys for obtaining this are the separated distribution of the frequency and phase of the master clock, and the detailed design of self-phase-adjustment circuits. The basic idea of the method is described, with emphasis on design formulae for clock signal delay times. Bipolar clock LSIs have been designed and tested. A clock skew time of ±50 ps has been obtained with an adjustable phase range of 3.7 ns