Programming Efficiency of Stacked-Gate Flash Memories with High-κ Dielectrics

Author

Chen, Y.Y. ; Chien, C.H. ; Kin, K.T. ; Lou, J.C.

Author_Institution

Energy & Resources Laboratories, Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu, Taiwan 310, R. O. C.; Computer Science & Information Engineering, Yuanpei Institute of Science and Technology, 306, Yuan Pei Road,

fYear

2006

fDate

10-13 Jan. 2006

Firstpage

302

Lastpage

305

Abstract

The programming efficiency of high-permittivity (κ) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-κ IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical 10μs programming time. However, the effect of high-κ TDs was quite different when compared with high-κ IPDs. High-κ TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under 10μs programming time by choosing HfO2as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-κ IPDs and TDs were suitable for next-generation NAND- and NOR-type stacked-gate flash memories, respectively.

Keywords

Channel hot electron injection; Dielectric losses; Dielectric substrates; Flash memory; Hafnium oxide; Laboratories; Medical simulation; Nonvolatile memory; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Technologies - Nanoelectronics, 2006 IEEE Conference on

Conference_Location

Singapore

Print_ISBN

0-7803-9357-0

Type

conf

DOI

10.1109/NANOEL.2006.1609734

Filename

1609734