Hazard checking in pipelined processor designs using symbolic model checking

The high speed requirements on today´s processors can be met by pipeline architectures, but pipeline structures cause hazards, which are their main drawback. In principle there are two ways to handle hazards: the compiler avoids hazard-causing code sequences or the hardware treats the hazard situations. We propose a method which allows the computation of all code sequences that cause control hazards. Our method can be divided into two steps. First we model the relevant behavior of the processor as a finite state machine (FSM). The modeling is carried out by an abstraction of the behavioral description of the processor which preserves the properties that are relevant for hazard checking. In the second step we determine the hazard-causing code sequences by applying symbolic model checking. In contrast to other model checking tools, which compute a single counter example only, our model checker allows the generation of all hazard-causing code sequences