Self-testing of S-compatible test units in user-programmed FPGAs

Author

Tomaszewicz, Pawel ; Krasniewski, Andrzej

Author_Institution

Inst. of Telecommun., Warsaw Univ. of Technol., Poland

Volume

1

fYear

1999

fDate

1999

Firstpage

254

Abstract

A method for the development of a test plan for BIST based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone. Logic cones that satisfy single-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. The number of test blocks corresponds to the number of test sessions. For the presented algorithm of computing logic cones, a tool was developed. The presented experimental results are used to develop heuristic rules that control the logic cone merging process

Keywords

built-in self test; field programmable gate arrays; logic testing; reconfigurable architectures; BIST based exhaustive testing; S-compatible test units; application-dependent testing; built-in self-testing; heuristic rules; in-system reconfigurable FPGA; logic cone; single-generator compatibility requirement; test block; test plan; test sessions; user-programmed FPGAs; Automatic testing; Built-in self-test; Decision support systems; Field programmable gate arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROMICRO Conference, 1999. Proceedings. 25th

Conference_Location

Milan

ISSN

1089-6503

Print_ISBN

0-7695-0321-7

Type

conf

DOI

10.1109/EURMIC.1999.794477

Filename

794477