VHDL description and high-level synthesis of an ATM layer circuit

In order to manage the higher complexity of VLSI chips and to reach shorter design cycles, the design effort becomes increasingly focused on higher levels of abstraction. We describe the design and the modeling of a high speed telecommunication circuit, an ATM Switch Controller (ASC) using a behavioral VHDL description. The VHDL description is simulated and synthesized with a commercially available High-Level Synthesis (HLS) tool. Advantages of this design method are discussed and the results of the synthesis are presented