Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations

In this paper we present an register transfer level (RTL) concurrent error detection (CED) technique targeting hardware implementations of elliptic curve cryptography (ECC). The proposed mixed hardware- and time-redundancy based CED techniques use the mathematical properties of the underlying Galois field as well as the ECC primitives to detect both soft errors and permanent faults with low area overhead. Results for sequential implementations of GF multiplication and inverse operations yielded an area overhead of 30% and a time overhead of 120%.