Performance comparison of envelope detector for RFID applications

This paper presents the comparison study of the performance of two envelope detector circuits, implemented on Standard Cells 0.18 ¿ CMOS process. The envelope detector which represents one part of demodulator block for RFID applications was designed based on two methods. The first circuit is designed partly using doubler cells with the aim to minimize the power consumption. The second circuit is built using conventional NMOS and low threshold transistor. The performance of both envelope detector circuits have been investigated. The first circuit is expected to consume lower input power compared to the second circuit which less than 1 ¿W. A few constraints also discussed in designing both circuits.