Title :
Long chain digital MOS transistor optimal design
Author :
Spanoche, Sorin-Andrei
Author_Institution :
Fac. of Electron. & Telecommun., Politehnica Univ. of Bucharest, Romania
Abstract :
This paper presents a method for optimal transistor sizing in digital circuits that contain long chains of transistors. First a new analytical model for the delay time is presented. Second, this model is compared to other models previously available, including the standard RC mesh model. Using the new model, delay time estimation fits well on SPICE simulations even for a small number of transistors and with load in an extended range. This model is included in an delay optimization tool that leads to delay improvement of up to 20% for constant cell area
Keywords :
MOS digital integrated circuits; SPICE; circuit CAD; circuit analysis computing; circuit optimisation; delays; integrated circuit design; integrated circuit modelling; logic CAD; SPICE simulations; delay optimization tool; delay time estimation; digital circuits; long chain digital MOS transistor design; optimal transistor sizing; Added delay; Clocks; Delay effects; Delay estimation; Integrated circuit modeling; MOSFETs; Parasitic capacitance; Phase estimation; Switching circuits; Threshold voltage;
Conference_Titel :
Semiconductor Conference, 1995. CAS'95 Proceedings., 1995 International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-2647-4
DOI :
10.1109/SMICND.1995.495039
