Title :
An all digital phase-locked loop with modified binary search of frequency acquisition
Author :
Jou, Shyh-Jye ; Tsao, Ya-Lan ; Yang, I-Ying
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2
Keywords :
circuit CAD; digital phase locked loops; digital simulation; search problems; 1.2 mm; 250 to 500 MHz; DCO frequency range; HSPICE; digital phase-locked loop; digitally controlled oscillator; frequency acquisition; high frequency digital clock; modified binary search; modified binary search algorithm; phase acquisition; phase-lock time; Clocks; Detectors; Digital control; Filters; Frequency; Laser mode locking; Microprocessors; Phase detection; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814861