A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells

1-V ultra low-power SRAM circuit techniques are described for word-bit configurable memory macrocells. A shared bitline SRAM cell architecture with modified address assignment is proposed to reduce wasted memory-cell current to zero while suppressing the area penalty. For the new SRAM cell design, we devise a multiplexer-merged charge-transfer amplifier for high-sensitivity read operation and a bitline precharge scheme with an equalizing line for high-speed write-recovery operation. A 1 V operating 64 kb (2 kw/spl times/16 b/spl times/2) test chip was designed using a 0.35 /spl mu/m multithreshold-voltage CMOS (MTCMOS) logic process. The simulated power dissipation is 1/4 (486 /spl mu/W) that of the conventional 1-V word-bit configurable SRAM macrocell with a 13% area increase.