Author :
Takahashi, O. ; Adams, C. ; Ault, D. ; Behnen, E. ; Chiang, O. ; Cottier, S.R. ; Coulman, P. ; Culp, J. ; Gervais, G. ; Gray, M.S. ; Itaka, Y. ; Johnson, C.J. ; Kono, F. ; Maurice, L. ; McCullen, K.W. ; Nguyen, L. ; Nishino, Y. ; Noro, H. ; Pille, J. ; Ri
Abstract :
This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.
Keywords :
CMOS integrated circuits; copper; low-k dielectric thin films; silicon-on-insulator; Cell BE design; SOI; Si-SiO2; automated migration; cell broadband engine; chip area reduction; chip power reduction; cycle-by-cycle machine behavior; die micrograph; size 45 nm; size 65 nm; CMOS logic circuits; Delay; Engines; Frequency; Power measurement; Power supplies; Predictive models; Programmable logic arrays; Semiconductor device measurement; Timing;
