Mixed-swing quadrail for low power dual-rail domino logic

Author

Ramasubramanian, Bharath ; Schmit, Herman ; Carley, L. Richard

Author_Institution

SUN Microsyst., Sunnyvale, CA, USA

fYear

1999

fDate

17-17 Aug. 1999

Firstpage

82

Lastpage

84

Abstract

This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full adder cell show a 24% delay decrease and a 24% energy reduction for the mixed-swing topology compared to standard dual-rail domino. Energy and delay trends with supply voltage scaling are also presented for the adder cell. An 8-bit by 8-bit multiplier design with mixed-swing dual-rail domino adders is presented. Simulation results show this implementation to be 10% faster with an 18% energy savings.

Keywords

CMOS logic circuits; adders; delays; logic design; low-power electronics; multiplying circuits; 0.6 micron; 8 bit; HSPICE simulation; delay reduction; domino adders; energy reduction; full adder cell; low power dual-rail domino logic; mixed-swing quadrail; mixed-swing topology; multiplier design; supply voltage scaling; Adders; CMOS logic circuits; CMOS process; Circuit topology; Clocks; Delay; Logic gates; Space exploration; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

1-58113-133-X

Type

conf

Filename

799414