Modeling and automating selection of guarding techniques for datapath elements

While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal savings. Three new internal guarding techniques are presented in adders that increase energy savings up to 38% over existing external guarding techniques. This allows guarded evaluation to be effective at duty cycles as much as 20% higher than are currently practical. A modeling methodology is presented defining the energy and energy delay of a unit in a generic application space. These models can easily be incorporated into an automated selection technique to determine the optimal guarded implementation. This technique is tested on a DSP ASIP, increasing overall energy savings by preventing unnecessary guarding. The data is generalized and it is observed that guarding is most beneficial when the ratio of guarding transistors to driven computational transistors is 1/10 or lower.