Selective instruction compression for memory energy reduction in embedded systems

Proposes a technique for reducing the energy required by firmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed instructions so as to reduce the energy dissipated in memory accesses. Instruction decompression is performed on the fly by a hardware module located between processor and memory: no changes to the processor architecture are required. Hence, our technique is well-suited for systems employing IP (instruction processor) cores whose internal architecture cannot be modified. We describe a number of decompression schemes and architectures that effectively trade hardware complexity for memory energy and bandwidth reduction, as proved by experimental data collected by executing several sample programs.