Digital design with minimal number of scan flip-flops

Author

Mourad, Samiha

Author_Institution

Dept. of Electr. Eng., Santa Clara Univ., CA, USA

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

931

Abstract

In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The emphasis of the research is not on finding the (Minimum Feedback Vertex Set) MFVS set that makes the circuit acyclic, but rather a minimal set of vertices that opens long feedback loops while keeping the fault coverage within user-defined acceptable limit. The algorithm determines the vertex set to open loops of length K or higher. We applied the algorithm to several ISCAS-89 benchmark circuits. For K=1 and except for one circuit, the number of flip-flops to be scanned is the same or slightly higher than the previously published results. However as K increases, our results indicated that it is not necessary to determine the MFVS, since a reduction of the hardware overhead by about 50% corresponds to a fault coverage reduction of only 2% from its value for K=1

Keywords

automatic testing; circuit feedback; flip-flops; integrated circuit testing; logic CAD; logic testing; sequential circuits; ISCAS-89 benchmark circuits; circuit acyclic; digital design; fault coverage; fault coverage reduction; feedback loops; hardware overhead; partial scan design; scan flip-flops; user-defined acceptable limit; Automatic test pattern generation; Circuit faults; Circuit testing; Feedback circuits; Feedback loop; Flip-flops; Logic testing; Pattern analysis; Registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584538

Filename

584538