A system level performance model for asynchronous micropipeline circuits

Author

Oelmann, Bengt ; Tenhunen, Hannu

Author_Institution

Dept. of Electron., R. Inst. of Technol., Kista, Sweden

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

952

Abstract

In this paper we present how an asynchronous system, using micropipelines, can be modelled in a system level performance model. We have introduced structures for pipeline stages and feedback structures. The model has been used in order to find out at what complexity a micropipeline implementation can out-perform a synchronous one. We have also used it for examining if micropipelines can be used as an alternative to clock-gating as a method for saving power. Results from these simulations are presented and compared to measurements on a complex asynchronous circuit

Keywords

asynchronous circuits; integrated circuit modelling; pipeline processing; asynchronous micropipeline circuit; feedback structure; power saving; simulation; system level performance model; Application specific integrated circuits; Asynchronous circuits; CMOS logic circuits; Circuit simulation; Clocks; Integrated circuit modeling; Laboratories; Logic gates; Power system modeling; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584543

Filename

584543