Low power and hardware efficient decimation filter

This paper presents a novel implementation of low power and hardware efficient digital decimation filter. We use multi-stage multi-rate signal processing to design and implement poly-phase half-band FIR filters and a band-pass IIR filter. The band-pass IIR filter is realized by cascading six second order all-pass filters. The decimation filter is designed and simulated using Simulink, DSP blockset and Matlab. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The resulting decimation filter has a power reduction of 42% and a hardware saving of 61% compared to conventional decimation filters.