Title :
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS
Author :
Boulemnakher, M. ; Andre, Elisabeth ; Roux, Jean-Francois ; Paillardet, F.
Author_Institution :
STMicroelectronics, Crolles
Abstract :
A low-power 1.2 V pipelined ADC is implemented in a 65 nm CMOS process to achieve 10b resolution at 100 MS/s based on the use of a dedicated thin-oxide high-performance analog (HPA) MOS transistor. The pipeline ADC is composed of eight 1.5b pipelined stages followed by a 2b flash converter as the last stage. In order to optimize the power consumption, the capacitances and the bias current of each stage have been scaled down along the pipeline chain. Measurement results of this ADC revealed a SNDR of 59 dB with a power dissipation of 4.5 mW. The core occupies 0.07 mm2, and 0.1 mm2 with the reference.
Keywords :
CMOS analogue integrated circuits; MOSFET; analogue-digital conversion; low-power electronics; pipeline processing; CMOS process; flash converter; low-power pipelined ADC; power 4.5 mW; size 65 nm; thin-oxide high-performance analog MOS transistor; voltage 1.2 V; Bandwidth; Circuits; Frequency conversion; Latches; Low voltage; MOS capacitors; MOSFETs; Pipelines; Sampling methods; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523151