Title :
A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS
Author :
Benkeser, Christian ; Burg, Andreas ; Cupaiuolo, Teo ; Huang, Qiuting
Author_Institution :
ETH Zurich, Zurich
Abstract :
This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s required for HSDPA is achieved at 58 mW and an energy efficiency of 0.7 nJ/b/iter. The number of iterations versus input SNR, as determined by the implemented stopping criterion, and corresponding power measurements.
Keywords :
CMOS integrated circuits; VHF circuits; application specific integrated circuits; iterative decoding; low-power electronics; packet radio networks; radiofrequency integrated circuits; turbo codes; ASIC; CMOS; HSDPA turbo decoder; energy efficiency; frequency 246 MHz; high-speed downlink packet access; iterative decoding; power 58 mW; size 0.13 mum;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523158
